1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, the local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quiet a period of time, it is one of the most reliable and low-cost methods for fabricating device isolation region. However, there are still some drawbacks of the LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by isolation regions is especially difficult to avoid; thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing an oxide layer in the trench and on the substrate. Next, a chemical-mechanical polishing step is used to planarize the oxide layer and to form an STI region. Therefore, the problem induced by the bird's beak can be overcome. As line width becomes smaller and integration becomes higher, STI is an ideal and scaleable isolation technique.
FIGS. 1A through 1D are schematic, cross-sectional views of the conventional process for manufacturing an STI.
As shown in FIG. 1A, a substrate 100 is provided. There are a pad oxide layer 102 and a mask layer 104 on the substrate, and a trench 106 penetrate through the mask layer 104 and the pad oxide layer 102 and into the substrate 100. A liner oxide layer 108 is conformally formed on the bottom surface and a portion of the sidewall of the trench 106 in the substrate 100.
As shown in FIG. 1B, an insulating layer 110 is formed over the substrate and filling the trench 106. A densification step is used to increase the density of the insulating layer 110.
As shown in FIG. 1C, a chemical-mechanical polishing (CMP) step is used to planarize the insulating layer 110 until the surface of the mask layer 104 is exposed and to form an STI 112.
As shown in FIG. 1D, the mask layer 104 and the pad oxide layer 102 are removed in sequence.
When the CMP step is performed, since the insulating layer 110 is softer than the mask layer 104, the surfaces 114a and 114b of the STI 112 manifest dishing (as shown in FIG. 1C). Moreover, since the polishing rates are different between the dense region 116a and the thin region 116b of the STI 112, the recess of the surface 114b in the thin region 116b is deeper than that of the surface 114a in the dense region 116a. Therefore, the nonuniformity of the thickness of the STI affects the subsequent process. Additionally, the slurry reagent used in CMP can react with the wafer, and then the abrasive particles polish the rough surface. Since the abrasive particles scratch the surface to form microscratches, the bridging effect occurs in subsequent process.
To improve the dishing induced by CMP, many methods are developed, such as reverse mask technique and dummy pattern technique. But the methods mentioned above all require an increase in photolithography and etching steps. The process for manufacturing the STI is more complicated and the costs are increased.